Electronic circuits, such as integrated circuits, are used in a variety of products, from automobiles to smart phones to personal computers. Designing and fabricating these circuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of integrated circuit being designed, its complexity, the design team, and the integrated circuit fabricator or foundry that will manufacture the circuit. Typically, software and hardware “tools” will verify a design at various stages of the design flow by running software simulators and/or hardware emulators/prototyping devices. The verification processes then are used to identify and correct errors in the design.
Several steps are common to most design flows. Typically, the specification for the new circuit initially is described at a very abstract level as a logical design. An example of this type of abstract description is a register transfer level (RTL) description of the circuit. With this type of description, the circuit is defined in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. A register transfer level design typically employs a Hardware Description Language (HDL) (sometimes also referred to as hardware design language or hardware definition language), such as the Very high speed integrated circuit Hardware Description Language (VHDL) or the Verilog language. The logic of the circuit is then analyzed, to confirm that the logic incorporated into the design will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
Logic simulation is a tool used for functional verification. Designing hardware today involves writing a program in the hardware description language. A simulation may be performed by running that program on a computer. Such an electronic design simulator can determine what the various states of an electronic design would be when presented with some input stimulus. Simulators are commercially available such as the QUESTA family of simulators from Mentor Graphics Corporations of Wilsonville, Oreg.
Software-based simulation, however, may be too slow for large complex designs such as SoC (System-on-Chip) designs. The speed of execution of a simulator drops significantly as the design size increases due to cache misses and memory swapping. Emulation and prototyping significantly increase verification productivity by employing reconfigurable hardware modeling devices including emulators and prototyping devices. Field programmable gate arrays (FPGAs)-based emulators and prototyping devices rely on an actual silicon implementation and perform circuit verification generally in parallel as the circuit design will execute in a real device. By contrast, a simulator performs circuit verification by executing the hardware description code serially. The different styles of execution can lead to orders of magnitude differences in execution time. Examples of hardware emulators include the VELOCE family of emulators available from Mentor Graphics Corporation of Wilsonville, Oreg., the ZEBU family of emulators available from Synopsys, Inc. of Mountain View, Calif., and the PALLADIUM family of emulators available from Cadence Design Systems of San Jose, Calif.
The verification processes may also include debugging software programs. Today's system-on-chip (SoC) designs aren't just hardware anymore. Modern devices are delivered with significant amounts of software, including software stacks, middleware, boot code, and drivers. In the past, the creation of hardware circuit chips was separate from the creation of the software to be executed on those circuit chips, but today a SoC isn't complete until the intended software has been proven to work—and to work well—on the platform. A reconfigurable hardware modeling device such as an emulator or an FPGA prototyping device provides a clock cycle accurate model of a circuit design, enabling detailed timing analysis and accurate determination of throughput, latencies and response times. It can thus be used to build an environment for validating various aspects of the system prior to obtaining physical silicon.
For a system to produce a result or achieve a goal, several software programs are often needed to work together or in tandem. For example, one software program initializes the circuit while another software program provide stimuli for the circuit to perform a function. Under conventional technologies, a software program in a software stack cannot be executed and debugged in a reconfigurable hardware modeling device-based environment until all other software programs in the same software stack are completed. This can prolong the overall verification process. Moreover, hardware verification engineers also need to be able to model the impact of software as it interacts with the hardware. Software testbench models can replace software programs by generating the stimuli for circuit models in some circumstances. However, many software programs cannot be abstracted into testbench models. New technologies are needed to address these challenges so that software development can start at earlier stages and circuit designs can be can be taped out earlier.